Engineering Group, Engineering Group ASICS Engineering Shape the future of low power AI subsystems. Push the boundaries on features and performance.

Qualcomm Technologies

Audio products are designed to offer premium wireless connectivity, high levels of integration, immersive sound quality, and on-device AI for smart audio and context aware applications. a chip-within-a-chip HW block incorporating multiple always-on IP's, design execution within this group requires solving ground-breaking challenges and multiple power domain crossing issues. As we deliver to the premium tiers of the mobile, compute, automotive, and IoT markets, we strive to pioneer new and/or improved functionality and innovate to minimize power consumption. We are looking for an ASIC Design Engineer that will work with industry leading edge HW Design technology and processes and provide expertise for next generation initiatives.

As a leader in delivering ultra-low power solutions, there will also be an emphasis on power analysis and optimization. Develop micro-architecture and module specifications for digital audio and AI IP blocks including those that interface with the SoC Analyze performance, area, power, and system cost tradeoffs for different implementations Work with the design verification team to debug tests at the module, sub-system and SoC levels throughout the ASIC development cycle (pre and post-silicon) Work with the implementation team to review synthesis results, review power metrics and reach static timing closure Analysis with silicon debug team to correlate stated objectives for both function and power 2+ years of professional industry ASIC hardware design and/or implementation experience. ~ Verilog/VHDL RTL design languages and ability to write clean, readable, synthesizable RTL. ~ Experience with power analysis, power modeling and low power RTL design.





Experience with clock domain crossing techniques Power and performance experience with an audio IP core, DSP, various audio interfaces (I2S, PCM, SLIMbus, SoundWire, Audio Codec) and accelerators (low-power AI/ML inference).

Experience with design rule check (Spyglass, etc.), and/or Power analysis and simulation Scripting skills (Python , PERL, TCL or C) Knowledge of bus interface protocols (APB, AHB, AXI) C coding Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, or related work experience. Master's degree in Science, Engineering, or related field and 1+ years of ASIC design, verification, or related work experience. PhD in Science, Engineering, or related field.

If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [email protected] request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive advantages package is designed to support your success at work, at home, and at play. #

📌 Senior ASIC Design Engineer, Low Power AI (Markham)
🏢 Qualcomm
📍 Markham