Our client, a North American ASIC Services provider is looking for experienced Verification engineers to join their growing team in Ottawa to work on various Design projects for semiconductor clients across North America. You will work closely with architecture, RTL, verification, firmware, physical design, and IP teams to deliver complex, high-performance silicon. You will translate architectural requirements into synthesizable SystemVerilog and Verilog, taking ownership of assigned blocks from specification through front-end sign-off.

The role combines custom datapath and control logic with the integration of third-party protocol and PHY IP, with a strong focus on power, performance, area, and physical implementation. Configure and integrate protocol and PHY IP, including clocking, reset, status, and control interfaces. Implement CSR access, configuration sequencing, interrupts, and management logic in collaboration with the firmware team.

Develop timing constraints, analyse synthesis results, and work closely with physical design teams on partitioning, congestion, and timing closure.



Debug design issues alongside verification engineers and maintain explicit, accurate design documentation. Deliver reviewed RTL and synthesis handoffs in line with project milestones and front-end sign-off requirements. 10+ years of hands-on ASIC RTL design experience, with ownership through successful tape-out. ~ Strong experience with high-bandwidth datapaths, pipelining, multiplexing, and multi-clock design. ~ Strong understanding of CDC/RDC, reset sequencing, assertions, and static design checks. ~ Hands-on experience with synthesis, timing constraints, and timing-report analysis, with the ability to work with physical design teams to resolve issues. ~ Scripting experience using Python, Tcl, or similar languages to automate design flows. ~ Ability to take ownership of technical decisions, lead design reviews, and communicate risks, challenges, and progress clearly.

UCIe or other chiplet interconnect experience, including protocol-to-PHY integration and advanced packaging considerations.

📌 Senior ASIC RTL Design Engineer (Quebec)
🏢 European Recruitment
📍 Quebec