A specialist engineering consultancy supporting advanced ASIC, FPGA, and embedded systems development is partnering with a global technology company developing high-performance silicon for next-generation connectivity and networking applications. We are looking for a Senior ASIC RTL Design Engineer to join a long-term client engagement focused on an advanced I/O chiplet combining die-to-die connectivity with multi-protocol, high-speed I/O. You will work closely with architecture, RTL, verification, firmware, physical design, and IP teams, taking ownership of assigned design blocks from architectural specification through front-end sign-off.

The role combines custom datapath and control logic with the integration of third-party protocol and PHY IP, with a strong emphasis on power, performance, area, and physical implementation. Translate architectural requirements into clean, synthesizable SystemVerilog and Verilog RTL . Configure and integrate complex protocol and PHY IP , including clocking, reset, status, and control interfaces.

Implement CSR access, configuration sequencing, interrupts, and management logic in collaboration with firmware teams. Develop timing constraints, analyze synthesis results, and work closely with physical design teams on partitioning, congestion, and timing closure. Debug design issues in partnership with verification engineers and maintain clear, accurate technical documentation.





Lead design reviews and communicate technical risks, challenges, dependencies, and progress clearly. Deliver reviewed RTL and synthesis handoffs aligned with project milestones and front-end sign-off requirements. 10+ years of hands-on ASIC RTL design experience , including ownership of designs through successful tape-out. ~ Strong expertise in SystemVerilog and Verilog , with a track record of translating specifications into maintainable, production-quality RTL. ~ Strong understanding of CDC, RDC, reset sequencing, assertions, and static design checks . ~ Hands-on experience with synthesis, timing constraints, and timing-report analysis . ~ Experience working closely with physical design teams to resolve timing, congestion, and implementation challenges. ~ Scripting experience with Python, Tcl, or similar languages for design-flow automation. ~ Ability to take ownership of significant technical decisions, lead design reviews, and drive blocks through front-end sign-off. ~ Solid communication skills and the ability to work effectively across architecture, verification, firmware, physical design, and IP teams.

Experience with UCIe or other chiplet interconnect technologies , including protocol-to-PHY integration and advanced packaging considerations. By applying to this role you understand that we may collect your personal data and store and process it on our systems.

📌 Senior ASIC RTL Design Engineer (Canada)
🏢 USA Tech Recruit
📍 Canada