Senior ASIC Verification Engineer – SystemVerilog / UVM / High-Speed I/O / SoC / Chipsets We are currently partnered with a semiconductor technology organisation developing advanced I/O and chipset solutions that connect die-to-die interfaces with high-speed, multi-protocol I/O. The technology combines advanced interconnect standards, high-speed networking, switching, and embedded management capabilities. As part of their continued development of complex silicon solutions, they are looking to hire a Senior ASIC Verification Engineer to establish and execute verification strategies across blocks, subsystems, and chip-level functions.

Develop verification plans that map requirements to test scenarios, verification platforms, coverage goals, and sign-off criteria Translate architectural and design requirements into measurable verification objectives Verify configured IP and end-to-end connectivity across protocol and PHY interfaces Verify static switching configurations, protocol modes, data integrity, latency, throughput, reset behaviour, and recovery mechanisms By applying to this role, you understand that we may collect your personal data and process it in line with our privacy policy. #

📌 Senior ASIC Verification Engineer - SystemVerilog / UVM / High-Speed I/O / SoC / Chipsets (Canada)
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📍 Canada