02 Oct
|
CELERO COMMUNICATIONS
|
Quebec City
02 Oct
CELERO COMMUNICATIONS
Quebec City
Celero Communications, Inc. is seeking an ASIC Design Engineer to join our rapid-growing Ottawa team. You will design high-performance digital ASICs for optical communication systems, using Verilog/SystemVerilog and collaborating with DSP, SerDes, and analog teams.
You will drive from architecture through tapeout, perform synthesis and timing analyses, optimize for PPA, and develop automation scripts in Python/Tcl to streamline design flows in a startup setting.
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📌 Optical Dsp & Mixed Signal Asic Design Engineer Quebec City
🏢 CELERO COMMUNICATIONS
📍 Quebec City