FULL -TIME

- Multiple Levels

- US / Canada / India/Remote Nuvacore is building ground-up CPU silicon for next-generation compute workloads. As our CPU Performance Modeling Lead, you will own the performance modeling infrastructure and methodology that drives every architectural decision we make — from early pathfinding through tape-out and post-silicon correlation

THE ROLE

- Design, develop and own Nuvacore’s cycle-accurate CPU performance simulator — its architecture, fidelity, and long-term roadmap — as the authoritative reference model for the design team.

Experience developing trace-based and execution-driven CPU performance simulators.

- Lead microarchitectural exploration across all major CPU domains: frontend (fetch, decode, branch prediction), out-of-order engine (rename, dispatch, execution), and memory subsystem (caches, prefetchers, TLBs, coherence).

- Drive model-to-RTL correlation through all execution phases; own debug and resolution of performance miscorrelation between the performance model, RTL simulation, and post-silicon results.

- Collaborate closely with design, verification, compiler, and system software teams to align architecture decisions with implementation constraints and software stack realities.

- Mentor engineers across the performance team; provide technical leadership on modeling methodology, simulation infrastructure, and analysis tooling.

- Contribute to IP development through patents and, where applicable, external publication

WHAT YOU'LL OWN

- Performance model: Cycle-accurate C++ simulator — architecture, calibration, and correlation against RTL and silicon.

- Workload analysis: Benchmark characterization (SPEC, GeekBench, AI/ML, cloud, client traces) and bottleneck identification.

- Microarch exploration:



PPA trade-off studies and feature proposals across the full CPU pipeline — frontend through memory subsystem.

- Cross-team alignment: Architecture-to-implementation bridge: design, verification, compiler, and OS/system software partners

Requirements — Must Have

- MS in Computer Architecture, Computer Engineering, or related field (PhD preferred).

- 20+ years (Lead) or 8+ years (ICs) in CPU microarchitecture and/or performance engineering.

- 20+ years (Lead) or 8+ years (ICs) of hands-on experience with cycle-accurate C++ CPU performance simulators (e.g. gem5 or equivalent in-house tools).

- Deep expertise in at least one of: branch prediction, fetch/decode, rename/dispatch, OOO execution, memory subsystem, or prefetchers.

- Strong C++ and Python / Perl skills; ability to write and analyse assembly for microarchitectural test cases.

- Proven track record driving performance from pathfinding through silicon (RTL correlation and/or post-Si debug).

- Experience in RISC-V or ARM64 or x86 ISA.

- Solid track record in identifying ideas to improve power/performance/area (PPA) of CPUs.

Requirements — Nice To Have

- Experience with compiler optimisations and hardware/software co-design.

- Published work or filed patents in CPU performance or microarchitecture.

- Prior principal-level role at a CPU design organisation.

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.

📌 CPU Performance Modeling (Lead & ICs) (Canada)
🏢 NUVACORE
📍 Canada