Join Infosys as a Memory Team Layout Engineer and contribute to cutting-edge memory design in Vancouver, BC. Collaborate with circuit teams to optimize layouts and drive innovation in memory technology. This role requires a minimum of 5 years of experience in compiler and custom memory layout design, with a robust background in memory architectures.

You'll engage directly with registers and memory data path layout engineers, ensuring the creation of optimal layouts based on provided schematics. Key Responsibilities:

- Collaborate with circuit engineering teams for layout optimization
- Design memory leafcell libraries from scratch
- Work on advanced memory architectures and technologies
- Ensure compliance with DRC, LVS, and ERC through physical verification
- Utilize Cadence Virtuoso for layout editing and optimization Requirements:
- Bachelor's degree or equivalent experience required
- Minimum 4 years in Information Technology
- 5+ years in compiler/custom memory layout design
- Experience with Finfet technology and layout design
- Must be willing to relocate to Vancouver, BC Leverage your expertise in memory technology and design to make a notable impact at Infosys in Vancouver.

📌 Memory Team Layout Engineer in Vancouver
🏢 Infosys
📍 Vancouver