Ciena leads in high-speed connectivity and is hiring for a mixed-signal IC design role in Ottawa. You will work on custom macros within an ASIC flow, contributing to analog-digital timing handoff and IP integration in a collaborative engineering setting.
The position requires a degree in electrical or computing engineering and hands-on experience with Cadence tools, Verilog/RTL, place-and-route, and timing analysis. Strong communication and Linux/Windows fluency are valued.