Senior Design Verification Engineer (Vancouver)

Senior Design Verification Engineer (Vancouver)

02 Oct
|
Diligent Tec
|
Vancouver

02 Oct

Diligent Tec

Vancouver

Company Description Diligent Tec, Inc. is a technology consulting firm specializing in advanced semiconductor and electronic design services. The company partners with leading organizations to deliver high-quality engineering solutions across the full product development lifecycle.

Diligent

Tec, Inc. focuses on complex digital design and verification challenges, offering expertise in cutting-edge architectures and verification methodologies. Team members collaborate in a technically rigorous workplace that values precision, innovation, and continuous learning. The company supports flexible work models to attract and retain highly skilled engineering professionals.

We are looking for an experienced Design Verification Engineer for a contract role with one of our direct clients in Vancouver, BC .

Canadian Citizens, PR holders, and candidates with valid Canadian Work Permits are encouraged to apply. US Citizens who are currently in the USA and are genuinely willing to spend the initial 1 month in Vancouver.

Job Title: Design Verification Engineer

Experience: 6+ - 15

Location: Vancouver, BC, Canada - Initial 1 month Hybrid then after Remote

Job Type: Contract

Job Summary





We are looking for a Design Verification Engineer with strong experience in ASIC/SoC verification to develop and execute verification environments and ensure high-quality digital designs.

Responsibilities

- Develop verification environments and testbenches using SystemVerilog and UVM .
- Create and execute functional, regression, and constrained-random tests.
- Analyze functional/code coverage and drive coverage closure.
- Debug RTL and simulation failures and work with design teams to resolve issues.
- Verify protocols such as AMBA/AXI, PCIe, Ethernet , or similar interfaces.
- Automate testing and regression using Python, Perl, or Shell scripting .

Required Skills
- Strong SystemVerilog & UVM experience.
- Solid understanding of RTL, digital design, and ASIC/SoC verification .
- Experience with simulation tools such as VCS, Xcelium, or Questa .
- Strong debugging and scripting skills.
- Bachelor's/Master's degree in Electrical, Electronics, or Computer Engineering .

Interested/available? Please reply with your updated resume + the following:

Name:

Current Location:

Work Authorization:

Years of Experience:

Relevant DV Experience:

Availability:

Expected Rate:

Phone:

📌 Senior Design Verification Engineer (Vancouver)
🏢 Diligent Tec
📍 Vancouver

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