USD 85 to 110 per hour, roughly USD 170,000 to 220,000 annualized at full utilization, ben…SystemVerilogUVM testbench architectureFunctional and code coverage closureSystemVerilog Assertions (SVA)Constrained random verificationVCS, Xcelium, or QuestaUSD 80 to 120 per hour, approximately USD 160,000 to 240,000 annualized at full utilizatio…SystemVerilog or VHDLVivado or QuartusTiming closure and SDC/XDC constraintsClock domain crossing designPCIe, Ethernet, or DDR interfacesOn chip debug (ILA or Signal Tap)USD 75 to 100 per hour, approximately USD 150,000 to 200,000 annualized at full utilizatio…SystemVerilog RTL designMicroarchitecture specificationLint and CDC signoff (SpyGlass or similar)Synthesis and static timing (Design Compiler or Genus)AMBA AXI, AHB,



or APB integrationLow power design intent (UPF)Own the link, not just the RTL — this role targets engineers who have taken high-speed int…SystemVerilogPCIe/CXLAXI/AMBACDCDDR4Timing closureShip inference datapaths — this role targets engineers who understand the workload, not ju…SystemVerilogRTL DesignFixed-pointAMBA AXISynthesisTiming closureOwn testbench architecture end to end — this role targets engineers who build verification…UVMSystemVerilogSVAAMBA/AXICoverage ClosurePython/TCL

📌 Senior FPGA Design Engineer, RTL to Timing Closure (Toronto)
🏢 ShawSilicon
📍 Toronto