Celero Communications, Inc. is seeking a Principal High-Speed Analog Layout Design Engineer to lead the layout of complex analog/mixed-signal IP blocks for next‑gen optical communication systems in Ottawa.
You will mentor junior engineers and collaborate with CAD/PDK teams to ensure first‑pass silicon success. In this hands‑on role, you will drive floorplanning, LVS/DRC checks, and layout verification using industry tools, while guiding cross‑functional teams across time zones and contributing
#J-18808-Ljbffr
📌 Senior High-Speed Analog Layout Engineer – IP Blocks Lead (Quebec City)
🏢 CELERO COMMUNICATIONS
📍 Quebec City
Reply to this offer
Impress this employer describing Your skills and abilities, fill out the form below and leave Your personal touch in the presentation letter.