Remote Design Verification Engineer Systemverilog/uvm Vancouver (Canada)

Remote Design Verification Engineer Systemverilog/uvm Vancouver (Canada)

30 Sep
|
Workada
|
Canada

30 Sep

Workada

Canada

NeurealM/ Microchip in Vancouver, BC, is seeking a Design Verification Engineer for a contract role. The candidate will develop verification settings and execute testbenches for ASIC/SoC designs, ensuring high-quality digital designs.

You will create functional, regression, and constrained-random tests, analyze coverage, debug RTL and simulation issues, and verify interfaces like PCIe and AMBA/AXI. Scripting skills in Python/Perl/Shell are required.
J-18808-Ljbffr

📌 Remote Design Verification Engineer Systemverilog/uvm Vancouver (Canada)
🏢 Workada
📍 Canada

Reply to this offer

Impress this employer describing Your skills and abilities, fill out the form below and leave Your personal touch in the presentation letter.

Subscribe to this job alert:

Get the latest job offers by email for: remote design verification engineer systemverilog/uvm vancouver (canada) / canada

Subscribe to this job alert:

Get the latest job offers by email for: remote design verification engineer systemverilog/uvm vancouver (canada) / canada