30 Sep
|
CELERO COMMUNICATIONS
|
Montreal
30 Sep
CELERO COMMUNICATIONS
Montreal
Celero Communications, Inc. is seeking an ASIC Design Engineer to join our rapid-growing Ottawa team. You will design high-performance digital ASICs for optical communication systems, using Verilog/SystemVerilog and collaborating with DSP, SerDes, and analog teams.
You will drive from architecture through tapeout, perform synthesis and timing analyses, optimize for PPA, and develop automation scripts in Python/Tcl to streamline design flows in a startup environment.
📌 Optical DSP & Mixed-Signal ASIC Design Engineer (Montreal)
🏢 CELERO COMMUNICATIONS
📍 Montreal