Celero Communications, Inc. is seeking a Principal High-Speed Analog Layout Design Engineer to lead the layout of complex analog/mixed-signal IP blocks for next‑gen optical communication systems in Ottawa.
You will mentor junior engineers and collaborate with CAD/PDK teams to ensure first‑pass silicon success. In this hands‑on role, you will drive floorplanning, LVS/DRC checks, and layout verification using industry tools, while guiding cross‑functional teams across time zones and contributing
📌 Senior High-Speed Analog Layout Engineer – IP Blocks Lead (Ottawa)
🏢 CELERO COMMUNICATIONS
📍 Ottawa
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