Principal High-Speed Analog Layout Design Engineer
Celero Communications is a fast-growing semiconductor startup developing high-performance coherent DSP technology for next-generation AI infrastructure. We recently announced a $275M Series C following the validation of the industry’s first 2nm coherent DSP silicon. Bloomberg also reported that Alphabet’s CapitalG has backed Celero at a $3B valuation. As we continue to grow, we’re hiring exceptional talent across the United States, Canada, and Argentina for a variety of exciting opportunities.We are seeking a
High-Speed Analog Layout Design Engineer
to drive the layout design of complex analog and mixed-signal IP blocks that are at the heart of our advanced optical communication systems. As a key member of the Analog & Mixed-Signal (AMS) design team, you will lead layout development of critical blocks such as ADCs, DACs, PLLs, and other high-performance analog/mixed-signal circuits. You will interface closely with circuit designers, CAD/PDK teams, and other layout engineers to ensure first-pass silicon success. This is a hands-on technical role ideal for someone who thrives in a fast-paced environment and enjoys mentoring others while contributing directly to cutting-edge chip development.Key Responsibilities
Lead and own the physical layout design of complex analog/mixed-signal macros (e.G., ADCs, DACs, PLLs), from floor planning through final verificationCollaborate closely with schematic designers to create optimal layout solutions considering performance, matching, symmetry, and reliabilityMentor and guide junior layout engineers/contractors across multiple time zones, enforcing best practices in layout design and verificationPerform and debug full hierarchy LVS, DRC, PERC, ERC, and other signoff checks using industry-standard tools (Pegasus, Calibre, etc.)Contribute to chip-level planning including top-level floor planning, block integration, power grid implementation, and signal routingParticipate in layout design reviews and provide technical leadership for layout quality, verification completeness, and schedule adherenceSupport automation initiatives through scripting and tool customization (SKILL, TCL, Python is a plus)Required Qualifications




Minimum 10+ years of hands-on analog/mixed-signal layout design experience and in advanced CMOS/FinFET technologiesProven track record of top-level integration IP layout macros and preparing IPs for handoff to Physical DesignProven leadership in owning major IP layout macros or full-chip-level layout at FinFET nodes (TSMC preferred)At least 1 year of experience with TSMC FinFET process nodes (N3, N5, N7, or N16)Deep understanding of device physics, layout-dependent effects (LOD, WPE, OSE, LDE, etc.), and their impact on circuit performanceStrong expertise in layout best practices for device matching, noise isolation, ESD protection, symmetry, and parasitic minimizationProficiency in floor planning, hierarchical block integration, routing strategy, and power/ground grid designExpertise with Cadence Virtuoso, Calibre, Pegasus, and other layout and verification toolsFamiliarity with layout verification flows, including LVS, DRC, PERC, Density, DFM, ERC, and Antenna rulesExperience working in cooperative environments with international and remote teamsStrong documentation and communication skills with the ability to clearly present layout trade-offs and status to cross-functional teamsExperience using revision control systems for layout design managementPreferred Qualifications
Exposure to optical or high-speed analog interfaces is a strong plusWorking knowledge of SKILL, TCL, or Python for layout automation or design flow optimizationProven ability to collaborate with international teams (U.S., Canada, Argentina)Robust organizational skills with high attention to detail and follow-throughAbility to multi-task and prioritize in a fast-paced, dynamic environmentProactive, eager-to-learn mindset with excellent problem-solving skillsWhat We Offer
The chance to play a foundational role at a high-growth semiconductor start-upExposure to a wide variety of cross functional teamsA collaborative,



international team culture where ideas and initiative are valuedThe opportunity to grow alongside Celero as we scale and shape the future of our industryA foundational role at a fast-growing semiconductor start-up shaping the future of AI and data center connectivityVoluntary Self-Identification
For government reporting purposes, we ask candidates to respond to the below self-identification survey. Completion of the form is entirely voluntary. Whatever your decision, it will not be considered in the hiring process or thereafter. Any information that you do provide will be recorded and maintained in a confidential file.As set forth in Celero Communications, Inc.’s Equal Employment Opportunity policy, we do not discriminate on the basis of any protected group status under any applicable law.If you believe you belong to any of the categories of protected veterans listed below, please indicate by making the appropriate selection. As a government contractor subject to the Vietnam Era Veterans Readjustment Assistance Act (VEVRAA), we request this information in order to measure the effectiveness of the outreach and positive recruitment efforts we undertake pursuant to VEVRAA. Classification of protected categories is as follows:A "disabled veteran" is one of the following: a veteran of the U.S. military, ground, naval or air service who is entitled to compensation (or who but for the receipt of military retired pay would be entitled to compensation) under laws administered by the Secretary of Veterans Affairs;
or a person who was discharged or released from active duty because of a service-connected disability.A "recently separated veteran" means any veteran during the three-year period beginning on the date of such veteran's discharge or release from active duty in the U.S. military, ground, naval, or air service.An "active duty wartime or campaign badge veteran" means a veteran who served on active duty in the U.S. military, ground, naval or air service during a war, or in a campaign or expedition for which a campaign badge has been authorized under the laws administered by the Department of Defense.An "Armed forces service medal veteran" means a veteran who, while serving on active duty in the U.S. military, ground, naval or air service, participated in a United States military operation for which an Armed Forces service medal was awarded pursuant to Executive Order 12985.
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📌 Principal High-Speed Analog Layout Design Engineer (Riviere-des-Prairies—Pointe-aux-Trembles)
🏢 CELERO COMMUNICATIONS
📍 Riviere-des-Prairies—Pointe-aux-Trembles