Synopsys Inc in Ottawa is seeking an experienced ASIC Digital Verification Engineer with a solid background in SystemVerilog and UVM to verify complex ASIC designs, including next-gen HBM products.
You will develop verification plans, debug testbenches, automate flows with Python or Perl, and contribute to design reviews. Join a cooperative team delivering high‑quality silicon and advancing verification methodologies.
📌 Senior Asic Verification Engineer – Systemverilog & Uvm Montreal
🏢 Synopsys
📍 Montreal
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