Elevate your career as a Design Verification Engineer in Vancouver, BC, with a blend of hybrid and work from home options. Leverage your extensive experience in ASIC/SoC verification to ensure superior digital design quality. In this pivotal role, you will develop and execute verification environments using industry-standard tools like SystemVerilog and UVM.

Your tasks will involve creating functional tests, debugging simulation failures, and verifying complex protocols. You'll also be responsible for automating testing via scripting languages. Key Responsibilities:
Design verification settings with SystemVerilog and UVM
Execute and analyze functional regression tests
Debug RTL and collaborate with design teams
Confirm protocol accuracy for AMBA/AXI, PCIe, Ethernet
Automate test processes using Python or Shell scripting Requirements:
Robust proficiency in SystemVerilog and UVM
Solid grasp of ASIC/SoC verification methodologies
Experience using tools like Xcelium or Questa
Demonstrated debugging and scripting capabilities
Degree in Electrical, Electronics, or Computer Engineering Apply your verification expertise to advance digital design excellence in our team.

📌 Expert Design Verification Engineer Role Vancouver (Canada)
🏢 TetriQ Solutions
📍 Canada