Asic Design Verification Engineer - Display (Up To Staff) - $124,200 - $174,200 A Year (Winnipeg)

Asic Design Verification Engineer - Display (Up To Staff) - $124,200 - $174,200 A Year (Winnipeg)

28 Sep
|
Qualcomm
|
Winnipeg

28 Sep

Qualcomm

Winnipeg

ASIC Design Verification Engineer role focusing on next-generation Display Processors for various markets. Requires robust skills in C/C++, OOP, hardware verification languages (SystemVerilog, UVM), HDLs (Verilog, SystemVerilog), digital circuits, and scripting languages.

📌 Asic Design Verification Engineer - Display (Up To Staff) - $124,200 - $174,200 A Year (Winnipeg)
🏢 Qualcomm
📍 Winnipeg

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