Job Summary

EPIC ASIC is a Toronto-based semiconductor design company delivering end-to-end ASIC and SoC development, from architecture and RTL through tapeout and production. Our team brings extensive experience in developing advanced silicon solutions and supporting clients throughout the product development lifecycle.

We work on challenging designs spanning high-performance computing, custom ASICs, high-bandwidth data movement, power optimization, and hardware for AI and datacenter infrastructure. Our engineers collaborate across disciplines to solve demanding technical problems while balancing performance, power, area, reliability, and time-to-market.

At EPIC ASIC, we value technical excellence, collaboration, and practical engineering. We are building a team of engineers who enjoy working at the forefront of semiconductor technology and taking designs from concept through working silicon.

EPIC ASIC and our clients are seeking a Hardware / Performance Architect to own micro-architecture and performance modelling for a large, regular compute-array inference ASIC. You turn system-level intent into block specs the RTL and compiler teams can build against.

What you will do




Define micro-architecture for compute array, memory subsystem and chip-to-chip interconnect; write block-level specs
Build and maintain the performance model (Python/C++) and the bit-accurate C/golden model; correlate against RTL and FPGA
Run PPA trade-offs (area, power, bandwidth, latency) on a 5nm-class node with GDDR-class memory and PCIe Gen6-class SerDes
Co-design with the compiler team: instruction set, static schedule format, memory map
Technical lead on architecture reviews with our design-service partners

What we are looking for
MS/PhD EE/CE; 10+ years in GPU, AI accelerator, network or CPU architecture
Shipped silicon where you owned a major block or subsystem spec
Robust in performance modelling, memory hierarchy and interconnect bandwidth/latency analysis
Working knowledge of transformer / MoE inference dataflow

Nice to have
Dataflow, spatial or statically scheduled architectures (Groq, Cerebras, Tenstorrent, SambaNova-style)
Chiplet / UCIe, multi-die system partitioning

Pay: $120,000.00-$140,000.00 per year

Work Location: In person

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