Advance your career with BTA Design Services as a Senior I/O Chiplet RTL Design Engineer, preferably based in Ottawa, Canada. Your extensive experience in RTL design will be crucial for delivering high-speed I/O solutions.

In this prominent role, you'll take ownership of translating architecture into synthesizable RTL, overseeing end-to-end design with a transparent focus on power, timing, and integration of third-party IP. Collaboration across various engineering teams is essential to ensure consistency in design quality and performance.

Key Responsibilities:
• Define specifications and budgets for block micro-architecture
• Configure static-switch fabrics and develop pipelined datapaths
• Write design assertions and manage verification processes




• Work with physical design for effective timing closure
• Conduct detailed timing report analysis to resolve issues

Requirements:
• Minimum of 10 years of ASIC RTL design experience
• Proficiency in SystemVerilog and Verilog
• In-depth knowledge of high-bandwidth designs and interfaces
• Hands-on experience with design checks and synthesis
• Scripting abilities to optimize design workflows

Join BTA to tackle today's connectivity challenges and shape the future of chiplet engineering.
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📌 Experienced RTL Chiplet Design Engineer (Quebec City)
🏢 Btadesignservices
📍 Quebec City