Join Ciena as an ASIC Design Engineer and play a crucial role in the development of high-performance optical networking solutions. Your focus will include synthesis, static timing analysis, and validation tasks.This engineering position at Ciena is dedicated to the front-end implementation of cutting-edge ASIC technology. You will execute critical functions like maintaining timing constraints and validating clock domain crossings for ASIC integration. Collaborate closely with various teams to enhance the overall design process in this fast-paced setting.Key Responsibilities:
Execute frontend ASIC implementation for various IP subsystems
Develop and maintain timing constraints to support integration
Perform logical equivalence checks between RTL and netlists
Validate clock domain crossings for top-level implementations
Create scripts for workflow optimizationsRequirements:
Bachelor’s in Electrical or Computer Engineering
Solid understanding of ASIC flows and timing validation
Familiarity with hardware description languages
Experience with multidisciplinary engineering teams
Solid project management skillsBring your expertise to Ciena and shape the future of high-speed connectivity.#J-18808-Ljbffr