Remote Design Verification Engineer (SystemVerilog/UVM) (Vancouver)

Remote Design Verification Engineer (SystemVerilog/UVM) (Vancouver)

27 Sep
|
Workada
|
Vancouver

27 Sep

Workada

Vancouver

NeurealM/ Microchip in Vancouver, BC, is seeking a Design Verification Engineer for a contract role. The candidate will develop verification environments and execute testbenches for ASIC/SoC designs, ensuring high-quality digital designs.

You will create functional, regression, and constrained-random tests, analyze coverage, debug RTL and simulation issues, and verify interfaces like PCIe and AMBA/AXI. Scripting skills in Python/Perl/Shell are required.

📌 Remote Design Verification Engineer (SystemVerilog/UVM) (Vancouver)
🏢 Workada
📍 Vancouver

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