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ROLE SUMMARY:
Own full-chip static timing analysis (STA) and timing closure for complex SoC designs, from

early design netlist through final signoff. Partner closely with PnR, synthesis/DFT, and CAD

teams to drive timing convergence, methodology improvements, and flow automation across the

business unit.

KEY RESPONSIBILITIES:
Timing Closure & Signoff

Own full-chip timing closure across setup, hold, and DRV (transition/capacitance/noise) signoff

Drive multi-corner/multi-mode (MMMC) timing convergence across PVT corners and modes

Analyze and resolve SI/crosstalk, OCV/POCV, and clock-related (skew, jitter, uncertainty) impacts on timing

Perform root-cause analysis of timing violations and drive fixes through ECO, PnR trials etc.

Generate, validate, and hand off ECOs to PnR PD teams; verify legalization and post-ECO QoR

Clock Architecture

Guide clock tree build strategy across multiple methodologies (H-tree, MSCTS/multi-source CTS, clock mesh)

Define clock structure and skew/latency targets in partnership with clock architecture and PD teams

Cross-Team Collaboration

Work with PnR engineers to drive timing convergence at each implementation stage (place, CTS, route, ECO)

Provide SDC (constraint) analysis, quality review, and feedback to design and synthesis teams

Feed back repeater/floorplan/design guidance across SoC based on timing analysis





Analyze run data and provide actionable feedback to PD execution teams

Collaborate across business units, CAD, and central methodology teams to define and drive requirements

Interface with other PPA (or equivalent) teams internal to AMD on cross-cutting timing topics

Methodology & Automation

Define and drive common STA methodology and signoff criteria across the business unit

Build automation to streamline design signoff checks, QoR tracking, and dashboard generation

Identify and adopt best practices from across AMD and industry to continuously improve flow/project best practices

Drive stage-by-stage improvements in competitiveness (PPA, turnaround time) of the AMD design flow

Communication

Organize and present complex technical timing data clearly and concisely to technical and management audiences

Document methodology, flows, and known issues for broader team consumption

REQUIRED QUALIFICATIONS:

BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field

Full chip timing experience preferred

Location:

Markham, ON

Benefits offered are described: AMD advantages at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

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📌 Static Timing Analysis / Full Chip Timing Engineer (Ontario)
🏢 AMD
📍 Ontario