Celero Communications is seeking a High-Speed Analog Layout Design Engineer to drive the layout of complex analog/mixed-signal IP blocks for advanced optical systems. You will lead floor planning through final verification, collaborating with circuit designers and CAD/PDK teams to ensure first-pass silicon success.
You will mentor other layout engineers across multiple time zones and contribute to top-level planning, power grid design, and signoff checks, while supporting automation through
📌 Lead High-Speed Analog Layout Engineer (Ahuntsic)
🏢 Emploive
📍 Ahuntsic
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