Ciena in Ottawa seeks a Digital ASIC Physical Implementation Engineer to shape large mixed-signal SoC designs for WaveLogic. You will drive the backend flow from netlist to GDSII, partnering with RTL and layout teams to optimize floorplans, power grids, and clock networks for best PPA.
We seek hands-on backend expertise, scripting for automation, and practical knowledge of UPF/SOCV/POCV, Calibre, and STA tools to ensure timing closure across complex designs.