Principal SerDes Design EngineerWe are looking for a SerDes Lead Designer, who is seeking an amazing chance delivering disruptive High Speed Interconnect Technology to power next generation AI. Candidate will have the opportunity to architect and design SerDes for next generation transceivers.What You Will DoDefine architecture, specifications, and circuit topologies for next-generation SerDesOverview development of system-level modelling, with behavioral models (e.G., MATLAB, SystemVerilog, Verilog-A) to analyze link budgets, equalization strategies and jitter budgetingDesign high-performance analog/mixed-signal circuits in advanced node technologiesDevelop and overview the design of critical blocks including RX/TX equalization (CTLE, DFE), High-speed PLLs, Phase interpolators, DLLs, TDCsImplement digitally assisted analog circuits, background calibration, and adaptive loops to improve Power, Performance, AreaOversee physical layout to minimize parasitics, device stress,



electromigration and process variation impactsOverview of the analysis of Signal Integrity and Power Integrity to achieve system-defined targetsLead lab validation, debugging and characterization of SerDes IPs within our state-of-the-art labCorrelate silicon measurements with simulated data, and lead performance optimization in the system environmentWhat You Will BringMaster's degree and/or PhD in Electrical Engineering or related fields with 10+ years of relevant experience in SerDes designProven record of taking high-speed SerDes design to tape-out and volume productionExperience in lab bring-up, characterization, and debugging designs that reach out productionMust have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes)Prior experience in cross-functional interaction to deliver IP and ensuring seamless integration in SOCsStrong communication and documentation skills

📌 Principal Serdes Design Engineer (Vancouver)
🏢 CELERO COMMUNICATIONS
📍 Vancouver