Drive innovation at Ciena as a Mixed Signal IP Integration Engineer, focusing on high-baud-rate optical modem technologies. This role offers hands-on engagement in custom mixed-signal design and integration within a thriving engineering environment.As a key player in the Ciena team, your role will involve the design and integration of complex mixed-signal macros in ASIC flows. You will utilize advanced electronics knowledge to address engineering design challenges,



contributing significantly to the development of integrated circuit solutions and standard cells for optimized performance.Key Responsibilities:Solve complex engineering design challenges with advanced VLSI techniquesDevelop representations for digital integration tasksGain insights into macro-level analog-digital interactionAid in the creation of design-for-test solutions and testing modelsFoster team-oriented engineering and design practicesRequirements:Degree in electrical or computing engineeringInternship or project experience relevant to the roleFamiliarity with analog design, extraction, and simulationExperience with Cadence toolsets and Verilog/RTL knowledgeAbility to program in Python or Cadence Skill languageLeverage your skills at Ciena to advance high-speed connectivity and mixed-signal design.

📌 Ciena High-Baud-Rate Integration Engineer (Riviere-des-Prairies—Pointe-aux-Trembles)
🏢 Socket.dev
📍 Riviere-des-Prairies—Pointe-aux-Trembles