Elevate your career with BTA Design Services as a Senior I/O Chiplet RTL Design Engineer in Ottawa, Canada. Work on cutting-edge multi-protocol I/O systems and collaborate with top engineering teams.This pivotal position requires extensive technical knowledge, focusing on synthesizing SystemVerilog and Verilog for high-speed I/O chiplet designs. As an engineer, you will define block specifications and integrate complex IP while ensuring power efficiency and performance. Participate actively in cross-functional teams and influence the design process from specification to sign-off.Key Responsibilities:Define micro-architecture and interface specificationsDevelop protocol multiplexers and configurable static-switch fabricsIntegrate protocol and PHY IP configurationsCollaborate with firmware on management logicWrite assertions and resolve design issuesRequirements:Over 10 years of ASIC RTL design experienceProficient in SystemVerilog and Verilog developmentStrong background in high-bandwidth datapathsExperience with complex IP integrationScripting skills in Python or TclLeverage your ASIC design skills to innovate leading-edge chiplet solutions at BTA Design Services.

📌 Senior I/O Chiplet Rtl Engineer Ottawa (Riviere-des-Prairies—Pointe-aux-Trembles)
🏢 BTA Design Services
📍 Riviere-des-Prairies—Pointe-aux-Trembles