25 Sep
|
CELERO COMMUNICATIONS
|
Canada
25 Sep
CELERO COMMUNICATIONS
Canada
Celero Communications, Inc. is seeking a Principal PLL Design Engineer in Ottawa to drive high-speed clocking design for next‑gen optical transceivers and SerDes.
The role focuses on designing and validating PLLs, VCOs and related analog blocks in advanced CMOS nodes, with hands-on lab bring-up and system-level validation. The ideal candidate has a Master’s or PhD in EE with 5+ years in PLL design, proficiency in Cadence Virtuoso and MATLAB, and solid documentation and cross‑functional
📌 Senior Pll Design Architect For High Speed Transceivers Ahuntsic (Canada)
🏢 CELERO COMMUNICATIONS
📍 Canada