Join Astera Labs as a Connectivity Verification Engineer and validate cutting-edge connectivity silicon for AI infrastructure. Utilize your expertise in UVM and C/C++ workflows to ensure product excellence.In the role of Connectivity Verification Engineer, you'll play a vital role in enhancing AI systems through thorough verification processes. This position necessitates building verification environments, translating design specs into test strategies, and applying your skills in debugging and collaboration with RTL designers. Your contributions will shape the future of rack-scale AI infrastructure.Key Responsibilities:Develop UVM verification environments utilizing SystemVerilogTranslate design specifications into actionable verification plansCreate comprehensive tests and analyze coverage dataAutomate testing workflows using Python or Perl scriptsCollaborate with engineers to debug across simulationsRequirements:Bachelor's degree in Electrical Engineering or similar2-5 years of SoC or silicon product verification experienceStrong skills in SystemVerilog and UVMExperience with directed and constrained-random testingEligible to work in CanadaMake an impact in AI connectivity validation as part of Astera Labs' cutting-edge team.

📌 Connectivity Verification Engineer - Astera Labs (Toronto)
🏢 Astera Labs
📍 Toronto