25 Sep
|
Synopsys
|
Ottawa
Synopsys Inc in Ottawa is seeking an experienced ASIC Digital Verification Engineer with a solid background in SystemVerilog and UVM to verify complex ASIC designs, including next-gen HBM products.
You will develop verification plans, debug testbenches, automate flows with Python or Perl, and contribute to design reviews. Join a collaborative team delivering high‑quality silicon and advancing verification methodologies.
📌 Senior ASIC Verification Engineer – SystemVerilog & UVM (Ottawa)
🏢 Synopsys
📍 Ottawa