EPIC ASIC is a Toronto-based semiconductor design company delivering end-to-end ASIC and SoC development, from architecture and RTL through tapeout and production. Our team brings extensive experience in developing advanced silicon solutions and supporting clients throughout the product development lifecycle.

We work on challenging designs spanning high-performance computing, custom ASICs, high-bandwidth data movement, power optimization, and hardware for AI and datacenter infrastructure. Our engineers collaborate across disciplines to solve demanding technical problems while balancing performance, power, area, reliability, and time-to-market.

At EPIC ASIC, we value technical excellence, collaboration, and practical engineering. We are building a team of engineers who enjoy working at the forefront of semiconductor technology and taking designs from concept through working silicon.

EPIC ASIC and our clients are seeking a RTL Design Engineer to design and deliver production RTL for the MPU compute die, working from architecture specs through to handoff for physical design.

What you will do





- Micro-architect and code SystemVerilog RTL for compute-unit array, control/sequencing, memory controllers and high-speed interface wrappers
- Integrate third-party IP: PCIe Gen5/6 controller + PHY, GDDR PHY, PLLs, management CPU subsystem.
- Own lint, CDC/RDC, synthesis constraints and timing closure feedback with the physical design team.
- Design for a highly replicated, tiled array: hierarchy, clock/reset distribution, DFT hooks, power intent (UPF).
- Support FPGA prototyping and bring-up of your blocks.

What we are looking for

- BS/MS EE/CE; 7+ years RTL design with at least two tapeouts on 16nm or below
- Expert SystemVerilog; solid on synthesis, STA concepts, CDC, low-power design
- Experience integrating high-speed SerDes-based interfaces or memory interfaces
- Comfortable working with remote design-service partners across time zones

Nice to have

- GPU / AI accelerator / switch ASIC datapath design
- Large-die (400 mm2+) experience; tiled or array-based floorplans

Pay: $120,000.00-$140,000.00 per year

Work Location: In person

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