A specialist engineering consultancy supporting advanced ASIC, FPGA, and embedded systems development is partnering with a global technology company developing high-performance silicon for next-generation connectivity and networking applications.We are looking for aSenior ASIC Verification Engineerto join a long-term client engagement focused on an advancedI/O chipletcombining die-to-die connectivity with multi-protocol, high-speed I/O. The technology brings together interfaces including UCIe, PCIe, Ethernet, static switching, and an embedded management subsystem.You will collaborate closely with architecture, RTL, verification, firmware, physical design, and IP teams to establish and execute verification strategies for complex silicon. The role spans high-speed datapaths and firmware-controlled management functions, with ownership extending from verification planning throughclosure, sign-off, and tape-out .Client identity and detailed program specifications will be shared confidentially during the interview process.Key Responsibilities:Develop comprehensiveverification plansmapping requirements to test scenarios, verification platforms, coverage goals, and sign-off criteria.Design and maintain reusableSystemVerilog/UVM verification environments, including sequences, agents, scoreboards, reference models, and assertions.Integrate vendorVIP and verification modelsto validate configured IP and end-to-end connectivity across protocol and PHY interfaces.Verify static-switch mappings, protocol modes, data integrity, latency, throughput, reset behavior, and recovery mechanisms.VerifyCSR access, boot and configuration sequences, sideband management, interrupts, and error-handlingin collaboration with firmware teams.Apply simulation, formal verification, connectivity checks, low-power verification, and hardware/software co-simulation where appropriate.Automate regressions, triage failures, and drivefunctional, assertion, and code coveragethrough closure,



including documenting justified exclusions.Review CDC/RDC findings with RTL designers and support gate-level sanity checks.Supportsilicon bring-upand debug issues identified during hardware validation.Communicate verification readiness, remaining technical risks, coverage status, and sign-off evidence clearly to engineering stakeholders.Key Qualifications:10+ years of hands-on ASIC verification experience, including ownership through verification closure, sign-off, and tape-out.Solid expertise inSystemVerilog and UVM, including constrained-random stimulus and reusable testbench architecture.Proven experience developing verification plans, defining coverage strategies, debugging complex failures, and driving verification closure.Hands-on experience withVIP integration, reference modeling, scoreboarding, and assertion-based verification .Strong understanding of multi-clock designs, reset behavior, protocol corner cases, and the limitations of simulation and static verification approaches.Strong scripting andregression automationskills, with disciplined test and configuration management practices.Ability to work independently, provide technical guidance and review others' work, and clearly communicate verification risks and sign-off evidence.Strong cross-functional communication skills and experience working with RTL, architecture, firmware, IP, and physical design teams.Nice to Have:Experience withUCIe, PCIe Gen6/Gen7, Ethernet PCS/FEC, 224G SerDes, or mixed-signal IP verification .Experience withformal model checking, connectivity verification, or power-aware simulation using UPF .Embedded processor verification experience, includingsecure boot, AXI/APB, register models, or firmware-driven testing .Experience withFPGA prototyping, emulation, or silicon bring-up .Experience using AI-assisted verification workflows within a controlled engineering and review process.By applying to this role you understand that we may collect your personal data and store and process it on our systems. For more information please see our Privacy Notice https://eu-recruit.Com/wp-content/uploads/2024/07/European-Tech-Recruit-Privacy-Notice-2024.Pdf#J-18808-Ljbffr

📌 Hybrid Asic Verification Engineer Position At Amd (Boucherville)
🏢 AMD
📍 Boucherville