Senior ASIC Verification Engineer – SystemVerilog / UVM / High-Speed I/O / SoC / Chipsets
We are currently partnered with a semiconductor technology organisation developing advanced I/O and chipset solutions that connect die-to-die interfaces with high-speed, multi-protocol I/O. The technology combines advanced interconnect standards, high-speed networking, switching, and embedded management capabilities.As part of their continued development of complex silicon solutions, they are looking to hire a Senior ASIC Verification Engineer to establish and execute verification strategies across blocks, subsystems, and chip-level functions. The role involves close collaboration with architecture, RTL, verification, firmware, physical design, and IP teams, with ownership extending through verification closure and tape-out.Key responsibilities
Develop verification plans that map requirements to test scenarios, verification platforms, coverage goals, and sign-off criteriaTranslate architectural and design requirements into measurable verification objectivesDesign and maintain reusable SystemVerilog/UVM verification settings, including sequences, agents,



scoreboards, reference models, and assertionsIntegrate third-party verification IP (VIP) and modelsVerify configured IP and end-to-end connectivity across protocol and PHY interfacesVerify static switching configurations, protocol modes, data integrity, latency, throughput, reset behaviour, and recovery mechanismsKey requirements
10+ years of hands-on ASIC design verification experienceProven ownership of verification activities through tape-out and formal sign-offExpert-level SystemVerilog and UVM experienceStrong understanding of constrained-random verification and reusable testbench architectureProven experience developing verification plans, defining coverage objectives, debugging complex failures, and driving verification closureHands-on experience integrating verification IP and developing reference models and scoreboardsKeywords
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📌 Senior Asic Verification Engineer – Systemverilog / Uvm / High Speed I/o / Soc / Chipsets Riviere Des Prairies—pointe Aux Trembles (Canada)
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