Drive innovation at Ciena as a Mixed Signal IP Integration Engineer, focusing on high-baud-rate optical modem technologies. This role offers hands-on engagement in custom mixed-signal design and integration within a thriving engineering environment.
As a key player in the Ciena team, your role will involve the design and integration of complex mixed-signal macros in ASIC flows. You will utilize advanced electronics knowledge to address engineering design challenges, contributing significantly to the development of integrated circuit solutions and standard cells for optimized performance.
Key Responsibilities:
• Solve complex engineering design challenges with advanced VLSI techniques
• Develop representations for digital integration tasks




• Gain insights into macro-level analog-digital interaction
• Aid in the creation of design-for-test solutions and testing models
• Foster team-oriented engineering and design practices
Requirements:
• Degree in electrical or computing engineering
• Internship or project experience relevant to the role
• Familiarity with analog design, extraction, and simulation
• Experience with Cadence toolsets and Verilog/RTL knowledge
• Ability to program in Python or Cadence Skill language
Leverage your skills at Ciena to advance high-speed connectivity and mixed-signal design.
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📌 Ciena High-Baud-Rate Integration Engineer (Ottawa)
🏢 Socket.dev
📍 Ottawa