Senior ASIC Verification Engineer – SystemVerilog / UVM / High-Speed I/O / SoC / Chipsets

We are currently partnered with a semiconductor technology organisation developing advanced I/O and chipset solutions that connect die-to-die interfaces with high-speed, multi-protocol I/O. The technology combines advanced interconnect standards, high-speed networking, switching, and embedded management capabilities.

As part of their continued development of complex silicon solutions, they are looking to hire a Senior ASIC Verification Engineer to establish and execute verification strategies across blocks, subsystems, and chip-level functions. The role involves close collaboration with architecture, RTL, verification, firmware, physical design, and IP teams, with ownership extending through verification closure and tape-out.

Key responsibilities

Develop verification plans that map requirements to test scenarios, verification platforms, coverage goals, and sign-off criteria

Translate architectural and design requirements into measurable verification objectives

Design and maintain reusable SystemVerilog/UVM verification environments, including sequences, agents,



scoreboards, reference models, and assertions

Integrate third-party verification IP (VIP) and models

Verify configured IP and end-to-end connectivity across protocol and PHY interfaces

Verify static switching configurations, protocol modes, data integrity, latency, throughput, reset behaviour, and recovery mechanisms

Key requirements

10+ years of hands-on ASIC design verification experience

Proven ownership of verification activities through tape-out and formal sign-off

Expert-level SystemVerilog and UVM experience

Solid understanding of constrained-random verification and reusable testbench architecture

Proven experience developing verification plans, defining coverage objectives, debugging complex failures, and driving verification closure

Hands-on experience integrating verification IP and developing reference models and scoreboards

Keywords

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📌 Senior ASIC Verification Engineer – SystemVerilog / UVM / High-Speed I/O / SoC / Chipsets (Ahuntsic)
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