- Perform functional verification of high-speed digital circuits using constrained random verification methodology- Model analog circuits behaviorally and perform mixed-level simulation of analog/digital circuits- Create product and technical documents- Prepare project plans and schedules- Provide technical guidance for verification tasks and resources within project teams- Collaborate with analog engineers, system engineers, and marketing to ensure designs meet customer and performance requirements- Work with Validation, Test, and Product Engineers to support end-product validation and qualification- Provide leadership, guidance, and mentoring to other engineers- Continuously improve design verification and productivity; review and enhance verification methodology- Contribute to digital subsystem development across definition, design, verification, and implementation- Help project teams meet milestones and objectives- Assist in setting company directions and driving best practicesRequirementsB.Sc. degree in Electrical or Computer EngineeringMinimum 5+ years relevant industry experience; preference for more than 7 yearsExpert knowledge in constrained random verification using UVM, OVM, AVM, or VMM methodologiesKnowledge and/or experience with object-oriented languages; SystemVerilog preferredExperience with Python, TCL, Perl,



or CWorking knowledge of PC and Unix/Linux operating systemsKnowledge of digital verification methodsStrong analytical and problem-solving skillsExcellent verbal and written communication skillsAbility to work independently and in a team environmentExcellent interpersonal and team skillsSelf-motivated and creativeWell organized, thorough, and detail orientedAbility to multitask and prioritize multiple simultaneous responsibilitiesCore CompetenciesDemonstrates expertise in constrained random verification methodologies, particularly using UVM, OVM, AVM, or VMM, alongside robust skills in digital verification methods and object-oriented programming with SystemVerilog. Capable of providing leadership and technical guidance while collaborating effectively with cross-functional teams to meet project milestones.Highest-signal resume keywordsConstrained Random VerificationUVM MethodologySystemVerilog ProgrammingDigital Verification MethodsProject LeadershipATS Optimization KeywordsHard SkillsConstrained Random VerificationUVM MethodologySystemVerilog ProgrammingPython ProgrammingTCL ProgrammingPerl ProgrammingC ProgrammingDigital Verification MethodsMixed-Level SimulationAnalog Circuit ModelingSoft SkillsAnalytical SkillsProblem-Solving SkillsVerbal Communication SkillsWritten Communication SkillsInterpersonal SkillsIndustry KeywordsElectrical EngineeringComputer EngineeringDigital CircuitsVerification MethodologyProduct ValidationTools & TechnologiesPC Operating SystemUnix Operating SystemLinux Operating System#J-18808-Ljbffr

📌 Senior Design/Verification Engineer (Winnipeg)
🏢 Jobtailor
📍 Winnipeg