Senior ASIC Verification Engineer – SystemVerilog / UVM / High-Speed I/O / SoC / Chipsets (Quebec City)

Senior ASIC Verification Engineer – SystemVerilog / UVM / High-Speed I/O / SoC / Chipsets (Quebec City)

22 Sep
|
USA Tech Recruit
|
Quebec City

22 Sep

USA Tech Recruit

Quebec City

Senior ASIC Verification Engineer – SystemVerilog / UVM / High-Speed I/O / SoC / Chipsets We are currently partnered with a semiconductor technology organisation developing advanced I/O and chipset solutions that connect die-to-die interfaces with high-speed, multi-protocol I/O. The technology combines advanced interconnect standards, high-speed networking, switching, and embedded management capabilities.
As part of their continued development of complex silicon solutions, they are looking to hire a Senior ASIC Verification Engineer to establish and execute verification strategies across blocks, subsystems, and chip-level functions. The role involves close collaboration with architecture, RTL, verification, firmware, physical design, and IP teams, with ownership extending through verification closure and tape-out.
Key responsibilities Develop verification plans that map requirements to test scenarios, verification platforms, coverage goals, and sign-off criteria
Translate architectural and design requirements into measurable verification objectives
Design and maintain reusable SystemVerilog/UVM verification environments, including sequences, agents, scoreboards,



reference models, and assertions
Integrate third-party verification IP (VIP) and models
Verify configured IP and end-to-end connectivity across protocol and PHY interfaces
Verify static switching configurations, protocol modes, data integrity, latency, throughput, reset behaviour, and recovery mechanisms
Key requirements 10+ years of hands-on ASIC design verification experience
Proven ownership of verification activities through tape-out and formal sign-off
Expert-level SystemVerilog and UVM experience
Robust understanding of constrained-random verification and reusable testbench architecture
Proven experience developing verification plans, defining coverage objectives, debugging complex failures, and driving verification closure
Hands-on experience integrating verification IP and developing reference models and scoreboards
Keywords By applying to this role, you understand that we may collect your personal data and process it in line with our privacy policy.

#J-18808-Ljbffr

📌 Senior ASIC Verification Engineer – SystemVerilog / UVM / High-Speed I/O / SoC / Chipsets (Quebec City)
🏢 USA Tech Recruit
📍 Quebec City

Reply to this offer

Impress this employer describing Your skills and abilities, fill out the form below and leave Your personal touch in the presentation letter.

Subscribe to this job alert:

Get the latest job offers by email for: senior asic verification engineer – systemverilog / uvm / high-speed i/o / soc / chipsets (quebec city) / quebec city

Subscribe to this job alert:

Get the latest job offers by email for: senior asic verification engineer – systemverilog / uvm / high-speed i/o / soc / chipsets (quebec city) / quebec city