- Lead or contribute to verification of 4–5 ASIC design blocks.
- Develop UVM-based verification environments, sequences, tests, debug, and coverage closure.
- Robust experience in SystemVerilog/UVM.
- Experience with PCIe, UCIe 2.0, and Ethernet protocols.
- Ability to independently own verification deliverables.
- Support customer collaboration in EST timezone.
Required Skills
- Strong SystemVerilog/UVM verification experience
- Knowledge and/or hands-on experience with:
- UCIe 2.0
- PCIe
- Ethernet
- Ability to own design blocks independently and drive verification closure
Responsibilities The DV team is expected to:
- Own verification of 4–5 design blocks per ASIC
- Develop and execute sequences
- Perform test development and debug
- Drive coverage collection and closure
- Own end-to-end verification execution for assigned blocks
- The customer will own the testbench infrastructure.