Senior ASIC RTL Design Lead in High-Speed I/O and Chiplets (Quebec City)

Senior ASIC RTL Design Lead in High-Speed I/O and Chiplets (Quebec City)

21 Sep
|
USA Tech Recruit
|
Quebec City

21 Sep

USA Tech Recruit

Quebec City

USA Tech Recruit is seeking a Senior ASIC RTL Design Engineer to own blocks from architectural specs through front-end sign-off. You will work on an advanced I/O chiplet integrating die-to-die connectivity with multi-protocol, high-speed I/O, collaborating with architecture, RTL, verification, firmware, PD, and IP teams.
You’ll drive microarchitecture, clocking, and power/area optimization for demanding silicon, including protocol and PHY IP integration and timing closure in a cooperative

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📌 Senior ASIC RTL Design Lead in High-Speed I/O and Chiplets (Quebec City)
🏢 USA Tech Recruit
📍 Quebec City

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