Elevate AI infrastructure at Astera Labs as a Digital Design Manager. Spearhead day-to-day DFT planning for cutting-edge signal-conditioning technologies.
In this leadership role, focus on advancing DFT architecture and enhancing silicon quality for high-speed connectivity solutions. You will collaborate with cross-functional teams, driving performance and yield improvements while mentoring emerging talent in the field. Your work directly influences next-generation AI systems.
Key Responsibilities: • Define comprehensive DFT plans for advanced packaging • Implement methodologies like scan and ATPG effectively • Collaborate on yield improvement and diagnostics • Mentor engineering team members during projects • Ensure effective communication of project risks
Requirements: • Bachelor’s degree in Electrical or Computer Engineering • 10-15 years in Digital Design or semiconductor testing • Expertise in DFT technologies and EDA tool usage • Understanding of ASIC design flow and fabrication • Familiarity with high-speed SerDes performance
Drive innovation for AI technologies at Astera Labs by leveraging your expertise.