21 Sep
|
FHLB Des Moines
|
Burnaby
21 Sep
FHLB Des Moines
Burnaby
Become a Senior SoC Design Engineer at Microchip Technology in Burnaby, BC, where innovation meets chance! Contribute to the design of advanced integrated circuits using your skills in Verilog and System Verilog.
At Microchip’s Data Center Solutions unit, we’re looking for professionals with 3 to 5 years in RTL design to join our team. In this role, you’ll focus on the design of digital integrated circuits, while ensuring alignment with key protocols. Quality communication and collaboration with architects and design teams will be essential to your success as you navigate complex technology solutions.
Key Responsibilities: • Design multi-million-gate digital integrated circuits • Define and document subsystem/block features • Support ASIC validation and perform debugging • Communicate designs and progress with key teams • Analyze and understand interface protocol standards
Requirements: • Degree in Electrical/Computer Engineering • 3 to 5 years related RTL Design experience • Knowledge of ASIC design methodologies • Familiarity with various design tools • Excellent teamwork and analytical skills
Shape your engineering career at Microchip, where your contributions matter.
📌 SoC Design Engineer Role at Microchip (Burnaby)
🏢 FHLB Des Moines
📍 Burnaby