Join Ciena as a Senior Team Lead Digital Verification Engineer in Ottawa, where you will implement cutting-edge verification strategies for the telecommunications industry. Leverage your expertise to guide and inspire your team. With a commitment to shaping the future of networking, at Ciena, you’ll lead a talented team focusing on the validation of the Wavelogic modem's Forward Error Correction (FEC) technology.

Drawing upon 10+ years of experience, your role encompasses developing cutting-edge test plans and optimizing collaboration among various engineering teams to achieve exceptional quality in digital verification. Key Responsibilities:
Oversee the development and execution of verification plans
Validate FEC functional blocks with formal and simulation techniques




Create and optimize testbench settings using System Verilog UVM
Mentor junior engineers on industry best practices
Update stakeholders on verification progress and risk assessments Requirements:
10+ years in digital verification engineering
Bachelor’s degree in relevant engineering fields
Proficiency in System Verilog, C/C++, UVM, and SVA
Strong communication and decision-making skills
Ability to mentor and lead engineers effectively Embrace this exceptional prospect at Ciena to influence the progression of telecommunications through your leadership in digital verification.

📌 Senior Team Lead Digital Verification Engineer Ottawa
🏢 Ciena
📍 Ottawa