Join Ciena as a Principal Engineer, specializing in Digital Verification within the telecommunications sector. Your expertise in FEC will guide critical validation efforts. As a key player on the Wavelogic modem team, you will bring extensive verification experience to validate functional blocks and develop comprehensive test plans.

Working closely with designers and engineers, you will ensure accurate simulation and implement cutting-edge verification strategies that enhance product performance. Key Responsibilities:
Read and interpret FEC architecture specifications
Develop verification and coverage test plans
Validate architectural FEC functional blocks
Create testbench environments using System Verilog UVM
Mentor junior engineers and guide their development Requirements:
Minimum 10 years in digital verification
Bachelor's degree in Engineering
Experience in C/C++, System Verilog, and related tools
Proven leadership in technical teams
Robust analytical and communication skills Shape the future of high-speed connectivity with your verification expertise at Ciena.

📌 Principal Engineer In Digital Verification Ottawa
🏢 Ciena
📍 Ottawa