Join Synopsys as an Expert ASIC Engineer specializing in physical design for test chips. You'll optimize creative designs and lead critical projects in a cooperative team. We’re looking for a talented ASIC Physical Design Engineer with 9+ years of proven experience in SoC and test chip implementations.

This role requires deep knowledge of the physical design flow and excellent collaboration skills. You will own the GDS release process and drive tool flow automation to enhance productivity. Key Responsibilities:
Contribute to physical design implementations for advanced chips
Own and optimize RTL-to-GDSII flow for better outcomes
Conduct static timing analysis and physical verification
Collaborate with various teams throughout the design process
Release supporting documentation for tape-out processes Requirements:
9+ years of ASIC physical design experience
Robust technical acumen in test chip methodologies
Familiarity with various verification flows
Advanced CAD tool expertise needed
Proven track record in leading technical efforts Utilize your leadership and design skills to champion innovations at Synopsys.

📌 Expert Asic Engineer At Synopsys Test Chip Design Ottawa
🏢 Synopsys
📍 Ottawa