Advance your career with a Senior ASIC Verification Engineer role at a specialist consultancy focused on connectivity solutions. Collaborate on cutting-edge I/O chiplet engineering.

In this position, you'll own ASIC verification processes from planning through to closure and tape-out, making your mark on next-gen silicon applications. Collaborating with RTL, architecture, and firmware teams, your 10+ years in ASIC verification will drive the success of high-speed data paths and management functions. Candidates with expertise in SystemVerilog and UVM will find this role uniquely rewarding.

Key Responsibilities:
• Develop and implement detailed verification plans
• Design advanced verification environments in SystemVerilog/UVM
• Validate static-switch mappings and protocol integrity




• Oversee regression testing and verification closure processes
• Communicate risks and verification readiness to stakeholders

Requirements:
• A minimum of 10 years in ASIC verification roles
• Expertise in SystemVerilog and UVM testbench development
• Proven history of successful verification closure
• Familiarity with multi-clock design challenges
• Solid communication and cross-team collaboration skills

Bring your skills in ASIC verification to elevate high-performance silicons at a leading technology company.
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📌 Senior Verification Engineer for Advanced Silicon (Quebec City)
🏢 USA Tech Recruit
📍 Quebec City