Elevate your career with Synopsys as a Senior Staff Engineer focusing on ASIC Digital Design. This role is crucial in pioneering high-speed SERDES PHY IP solutions while collaborating across multiple engineering disciplines.
At Synopsys, you will be a visionary leader with a passion for semiconductor innovation. With over eight years of experience, you'll manage high-performing design teams and drive complex digital projects. Your expertise will include synthesizable Verilog and System Verilog, guiding projects from specification to successful integration.
Key Responsibilities: - Collaborate with architects and cross-functional teams for IP delivery - Plan and drive phases of SERDES PHY IP design - Achieve optimal timing, performance, and power goals - Mentor team members to foster growth and innovation - Provide customer support for successful IP integration
Requirements: - Bachelor’s degree in Electrical Engineering - 8+ years in technical development - Proficiency in Verilog and System Verilog - Experience in front‑end design flows - Robust communication and collaboration skills
Shape the future of silicon IP with your leadership and technical expertise at Synopsys.#J-18808-Ljbffr

📌 Senior Staff Engineer For Asic Design Winnipeg
🏢 Synopsys
📍 Winnipeg