Package Design Engineer (IC/IP) (Canada)

Package Design Engineer (IC/IP) (Canada)

19 Sep
|
Collabera
|
Canada

19 Sep

Collabera

Canada

Company: Integrated Circuit and Software Testing

Title: Senior Staff Package Design Engineer - L4

Duration: 1-year contract-to-hire

Location: Ontario - Ottawa or Toronto preferred

Work Structure: Hybrid, 2-3 days if they are nearby client office ( Canada : Markham, Ottawa, Mississauga, Nepean and USA : Arizona, California, Colorado, Massachusetts, Minnesota, New York, North Carolina, Oregon, Texas, Vermont, Washington) but fully remote candidates anywhere in North America are acceptable as well .

Hours a Week: 40

Pay Rate: $70-80/hr (after conversion 160k-170k base + bonus and benefits)

Job Overview:

Synopsys is looking for 3 Senior Staff Package Design Engineers with extensive semiconductor package design experience. This person will work on the physical design, modeling, and optimization of packages used for IP test chips, ensuring the packages meet required performance specifications. The work begins with package design, modeling, and optimization and then progresses into mechanical and thermal modeling.

Package-design projects can take approximately 18 weeks or longer, and the engineer will support multiple test-chip package designs throughout the year. The role is highly hands-on and requires someone who can physically design and lay-out semiconductor packages rather than someone whose experience is limited to analysis or general hardware/PCB design. The official JD notes that the engineer will support approximately 3-5 SOC test-chip package designs per year and participate in early-stage optimization for SI and PI performance.

Reason for hiring: Synopsys is building a second “factory” team to support a recent,



more customized customer model for major hyperscalers/AI infrastructure customers.

Day-to-Day Responsibilities:

- Perform hands-on semiconductor package design and physical layout using computer-based design/EDA tools .
- Work through package design, modeling, and optimization before progressing into mechanical and thermal modeling.
- Collaborate during early design stages to define and optimize requirements for power integrity (PI) and signal integrity (SI), including areas such as bump maps.
- Extract models and analyze package substrate designs.
- Support approximately 3–5 SOC test-chip package designs per year.
- Coordinate different phases of the package design process and overall design flow.
- Use package-layout/design tools such as Cadence APD, Allegro, Design Force, and AutoCAD.
- Work with electromagnetic modeling and analysis tools.
- Troubleshoot complex package-design issues and provide regular project updates to the manager
- Work with a global engineering team and represent the organization on business-unit projects.

Must Haves:

- 8-10+ years of relevant professional design/engineering experience.
- 3-5+ years of specific, hands-on semiconductor package design experience.
- Strong hands-on physical package layout/design experience.
- Experience with package design/layout tools such as:
- Cadence APD (highly preferred)
- Allegro (highly preferred)




- Design Force
- AutoCAD
- Equivalent industry-standard package design tools may also be considered.
- Strong understanding of circuit and transmission-line theory.
- Experience with package model extraction and analysis.
- Bachelor's degree in electrical engineering, Electronic Engineering, or equivalent (Bachelor of engineering)

Nice to Haves:

- Strong Power Integrity (PI) experience
- Strong Signal Integrity (SI) experience
- Mechanical and thermal modeling experience.
- Experience supporting Soc test-chip package designs.
- Experience working across both Windows and Linux environments.
- Career background progressing from:
- Chip Design → Package Design
- Package Operations → Package Design
- Experience with 3D electromagnetic modeling tools such as HFSS or similar industry standard tools.

We may use AI-enabled and/or automated tools to support parts of our recruitment process, including application screening, interview scheduling, and candidate communications. These tools are used to enhance consistency and efficiency. All hiring decisions involve human review and are not based solely on automated processing. The Company offers a total rewards package in accordance with all applicable federal, provincial, and local laws and requirements. Benefit eligibility and offerings vary based on role, employment status, and work location. For contractor positions, benefits are limited to those entitlements and protections required by applicable law, which may include (as applicable) vacation pay, public holidays, leaves of absence, and other legally mandated benefits or payments.

📌 Package Design Engineer (IC/IP) (Canada)
🏢 Collabera
📍 Canada

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