Elevate your career with BTA Design Services as a Senior I/O Chiplet RTL Design Engineer in Ottawa, Canada. Work on cutting-edge multi-protocol I/O systems and collaborate with top engineering teams.
This pivotal position requires extensive technical knowledge, focusing on synthesizing SystemVerilog and Verilog for high-speed I/O chiplet designs. As an engineer, you will define block specifications and integrate complex IP while ensuring power efficiency and performance. Participate actively in cross-functional teams and influence the design process from specification to sign-off.
Key Responsibilities: • Define micro-architecture and interface specifications • Develop protocol multiplexers and configurable static-switch fabrics • Integrate protocol and PHY IP configurations • Collaborate with firmware on management logic • Write assertions and resolve design issues
Requirements: • Over 10 years of ASIC RTL design experience • Proficient in SystemVerilog and Verilog development • Robust background in high-bandwidth datapaths • Experience with complex IP integration • Scripting skills in Python or Tcl
Leverage your ASIC design skills to innovate leading-edge chiplet solutions at BTA Design Services.