Job Title: Design Verification Engineer

Client: NeurealM/ Microchip

Location: Vancouver, BC, Canada - Initial 1 month Hybrid then after Remote

Job Type: Contract

Job Summary

We are looking for aDesign Verification Engineerwith solid experience inASIC/SoC verificationto develop and execute verification settings and ensure high-quality digital designs.

Responsibilities
Develop verification environments and testbenches usingSystemVerilog and UVM.
Create and execute functional, regression, and constrained-random tests.
Analyzefunctional/code coverageand drive coverage closure.
Debug RTL and simulation failures and work with design teams to resolve issues.
Verify protocols such asAMBA/AXI, PCIe, Ethernet, or similar interfaces.
Automate testing and regression usingPython, Perl, or Shell scripting.

Required Skills
StrongSystemVerilog & UVMexperience.
Solid understanding ofRTL, digital design, and ASIC/SoC verification.
Experience with simulation tools such asVCS, Xcelium, or Questa.
Solid debugging and scripting skills.
Bachelor's/Master's degree inElectrical, Electronics, or Computer Engineering.
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📌 Design Verification Engineer Vancouver
🏢 Diligent Tec
📍 Vancouver